[Overview
| CDFVME] [Overview
| CDFVME]
| The Inner tracker of CDF is undergoing a major upgrade from the Run I,
4-layer, single-sided, 50K channel detector to the Run II configuration,
which has 5 layers of double-sided sensors (3 at 90 degrees and 2 small-angle
stereo) and 500K channels. (See the CDF Technical Design Report for full details.) Precision tracking near the interaction region has proved to be an extremely useful tool for a wide range of physics. It allows for the identification of particles with lifetimes of the order of 1 ps, ie particles containing b and c quarks, as well as taus. Simply being able to identify whether a jet contains a b quark enabled the discovery of the top quark in Run I. Some precision electroweak measurements, such as the branching ratio of Z-> b-bbar also require b-jet identification. Further, for a large range of plausible Higgs masses, the Higgs decays principally via H -> b-bbar. For practically all analyses studying the b sector directly, precision tracking is required to isolate a clean sample of b mesons or baryons. Combinatorial backgrounds in invariant mass distributions are too high for mass alone be the means of selecting a b sample. Requiring candidate tracks come from a common vertex, with the possible additional cut that this vertex is significantly separated from the primary vertex, results in samples with sufficient purity for most analyses. At CDF, direct production of b quarks occurs predominantly via gluon-gluon fusion, mostly at low momentum since there are more incident gluons at low energy. Typical Lorentz boosts are 2.5 to 4. Since the lifetime of the B mesons is 1.5 ps, the typical distance a B travels before decay is 1.5 mm. The Run I Silicon Vertex Detector (SVX and SVX') was 50 cm long. Since the interaction region had a Z (longitudinal) RMS of 30 cm, the detector covered less than one sigma of the luminous region. This translates into a single track acceptance of approximately 60%, averaged over all interactions, for particles travelling perpendicular to the beamline, falling off as shown here as the particle's direction becomes closer to the beamline. By extending the length of the silicon to approximately 90 cm, much of this lost acceptance can be regained. Current estimates from the Fermilab Accelerator Division put the luminous region's width at closer to 15 cm for Run II. The acceptance vs. track angle for this running condition is shown as the solid line in the above figure. This increase results in a 65% improvement in the geometrical acceptance for top events, and a 200% improvement in the rate of top events in which both b jets pass through the silicon. The Run I Silicon Detector was made up of 4-layers of single-sided sensors, providing measurements in the r-phi plane. The SVX II upgrade will include double-sided detectors which measure both r-phi and r-Z directions. There will be 3 planes with Z strips on the second side, and 2 with small-angle stereo (1.2 degrees to r-phi), allowing precision track segments to be constructed in both views, and matching the two into full 3-d tracks. In addition, a extra layer of silicon at larger radius, and two extra layers at high angles (ISL), will provide a means of linking track segments found using silicon-only with track segments from the outer drift chamber (COT). The following table shows a comparison between the Run I and Run II detectors.
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The Yale group is involved in the design, commissioning and operation of the data acquisition system serving the SVX II detector. This data acquisition system (DAQ) must meet much more severe requirements in Run II. In addition to handling a factor of 10 more channels , it must operate at significantly higher speeds. The bunch crossing rate at the Tevatron was one per 3 microseconds in Run I. Run II will start with a 396 ns bunch spacing, with plans to lower this to 132 ns. To accommodate this, a new front-end chip (SVX3 chip) was developed along with a highly-parallel, high-bandwidth DAQ system. The readout scheme is shown here. The system consists of 10 VME crates filled with modules described below. The system controller for the readout is the SRC (Silicon Readout Controller), which acts as the interface between the trigger system and the silicon DAQ. It responds to Level 1 Accept (L1A), L2 Accept (L2A) and L2 Reject (L2R) commands from the Trigger Supervisor. It flags errors to the Trigger Supervisor, and can throttle the DAQ system when it has run out of local (DAQ) buffers to store events. Commands from the SRC are passed to 4 crates of FIBs (Fiber Interface Boards), each of which contains a FIB Fanout module, which simply decodes the signals sent from the SRC and fans them out over a custom J3 backplane. The command path from the SRC to the FIB crates is optical, using HP Glinks (Gigabit serial links). The FIBs each control 2 Port Cards (PCs), which reside inside the CDF detector. Command to the PCs is over a copper cable, whereas the data comes back on a low-power, densely packed optical path (DOIM). Each Port Card controls 5 independent chains of SVX3 chips (to a maximum of 16 chips per chain). The data is read from each chain of SVX3 chips in parallel, with the chips readout serially on each chain, and sent to the FIB via the Port Card. It is then sent from the FIB via Glinks to 6 crates of VRBs (VME Readout Buffer), which are simply bulk memory used to store events waiting for a L2 trigger decision or waiting to be read into the Level 3 processor farm. This data is also split optically and sent to a Level 2 trigger processor called the SVT (Silicon Vertex Trigger). This trigger accepts tracks from Level 1 track--finding hardware based on the central drift chamber, and tries to link silicon hits to the tracks. If a match is found, the impact parameter of the track to the primary vertex is determined. This allows a trigger based upon finding displaced tracks to be implemented, and in particular, results in a b-jet trigger which does not rely upon the presence of a lepton. All told there are 3168 chips, 360 HDIs, 72 PCs, 36 FIBs, 4 FIB Fanouts, 36 VRBs, 4 VRB Fanouts and 1 SRC. |
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