Trigger supervisor 2   (TS_2) schematic page descriptions

Page1:  J1, J2 J0 and front panel connectors
        Includes ESD strips, Geographic address pin logic,
        the Power fusing, power LEDs, and the DC-DC
        converter for -5.2V power.
        
        Also LVDS receiver for front panel connections to a single 
        tracer in 'standalone mode'
        
Page2: Clock switching / buffering, Front panel switches w/debouncing
       for reset and single step clock.  Clock line 100 ohm
       terminations shown here.  Digital programmable delay lines are
       provided to provide phase adjustable clocks to the               Taxi transmitters ( see page 10 ).
     
Page 3: VME interface featuring the Cypress SVIC chipset.
        The LS123 both flashes the VME access lamp and initiates
        Xilinx programming after the SVIC configuration at power on.

Page 4: TS_2 'V_chip' ( Xilinx 4008 with serial prom )
        Handles board level registers and initialization.
        Unlike TS1, not involved in Data readout stream.
        ID-Prom also on this page.  The TS2 test connector shown is
        a special header for a mezzanine style breakout board as
        developed by U of Michiagan allowing many test connections to 
        logic analyzers in a small space.  JP20,22,23 are provided
        to provide for use of unallocated test positions on the 
        mezzanine card, and are of no concern in normal running.

Note: All other Xilinx FPGAs are 4013E PQ240 devices, configured as 2
daisy chains with parallel EPROMS.  There is provision for using larger
devices should the need arise.

Page 5: Level 1 state machine Xilinx chip.  Also shows its related 
        indicators/ displays and testpoints.
Note: Most testpoints are in the form of HP logic analyser compatible
      2x10 headers for easy access to 16 lines at the same time.

Page 6:  Level 2 machine with extras as above.  Also one of the 2
        configuration master devices so one eprom is here as well.
        EPROM U39 contains FPGA programming for L2, Readout,
        Misc and Level 1 chips.
Note: Testpin 'T9' if connected to ground will cause all seven segment
      displays to illuminate every segment.
      Jumpers JP31,32,33,and 34 control the behavior of leading zeros
      (shown or not) in each 2 digit display.
 
Page 7:  Readout machine with displays as above

Page 8: Calibration state machine chip with displays.  Another
        configuration master device with EPROM U50.  This Eprom
        holds configuration data for Calibration, Scheduler and the
        Fanout chips.

Page 9:  Scheduler state machine ( prioritizes and assembles TSI output           data into frames for fanout chip ) 
         JP24,27,27 allow the clock lines to be disconnected from the
         test connector for higher signal fidelity.

Page 10: Fanout xilinx chip and assosicated Taxi transmitter circuits.
         This chip allows TS data to be sent as 3 separate serial streams
         independently phase adjustable ( in 1/8 MC tick steps ).
         JP19,21,25 are provided to allow the taxis to run syncronously
         off of the main TS clock as a cautious provision.         

Page 11: Misc chip, this serves many control and data stream functions.
         JP11-18 allow for many connection options to our backplane
         reserve lines.  Also TS Error indicator.

Page 12: All J3 backplane connections with data buffers and
         differential ECL Fanouts for taxi data.  Also the J7,8,9
         front panel connectors for return crosspoint inputs.
         There are many jumpers to provide grounding options for the
         cable connections.

Page 13: TSI emulation section copied from the Testclk V7 board.
         Also nim input circuitry for the front panel lemo
         connectors.

Page 14: Additional bypass capacitors and ground pins.

--Thurston Chandler 9/98
  Yale CDF Group