FRED ( Global Level 1 descision board ) Schematic Page Descriptions

Page1:   J1, J2 J0 and front panel connectors
         Includes ESD strips, Geographic address pin logic,
         the Power fusing, and LEDs.
         Also RS-485 differential driver for front panel connections to 
         the TSI crate ( this is pin compatible with LVDS which will be used)
        
Page2:   Clock switching / buffering, Front panel switches w/debouncing
         for reset and single step clock.  Clock line 
         terminations shown here.  Digital programmable delay lines are
         provided to provide phase adjustable clocks to the multiple
         syncronous sections of this board.  While it only uses the MC
         frequency these delays allow us 5 clock 'edges' per cycle.
     
Page 3:  VME interface featuring the Cypress SVIC chipset.
         The LS123 both flashes the VME access lamp and initiates
         Xilinx programming after the SVIC configuration at power on.

Page 4:  TS_2 'V_chip' ( Xilinx 4008E with serial prom )
         Handles some board level registers, VME protocols
         and initialization. ID-Prom also on this page. 
         Includes 2, 2x10 test headers for HP logic analysers.

Note:    All other Xilinx FPGAs are 4008E PQ208 devices, configured as
         2 daisy chains with parallel EPROMS.  There is provision for
         using larger devices should the need arise.

Page 5:  XC1,2,3 input presorting chips with EPROM.  These chips take
         Prefred and master clock system data from the input bufers
         and format it for use in the rest of the high speed data path.

Note:    Eprom U24 can be loaded with 2 separate programs for these chips
         which can be selected between at initialization time.

Page 6:  High speed data ECL <-> TTL conversion page.  Required for
         communication between AMCC crossbows and the rest of FRED.
         Includes pulldown/terminations for all 392 ECL lines.
       
Page 7:  AMCC crossbow chips configured as 64x64 crosspoint switch.
 
Page 8:  Level 1 FIFO chips.  These IDT fifo chips delay fred and prefred
         data to syncronize it with the descision returned from the
         TS > TXPT > TRACER link.  The number of clocks to delay is                 
         programmable.  The FRED Misc chip controls all configurations.

Page 9:  Fred 'Level 2 Buffers' discrete dual port memory for storing
         fred's data awaiting DAQ readout of accepted events.  This
         page amounts to 6 32bit words of data for each of the 4 buffers.
         The additional information needed by level 3 is stored in 
         the Misc chip which provides linear addressing of each buffer.

Page 10: High speed data path SRAM array.  The trigger table is stored
         here and interacts with the data between the crosspoint and 
         prescale stages.  Multiple buffers and transcievers allow for
         ram readback and programming via VME.

Page 11: Scalar output drivers and connectors.  the 392 bits of fred
         data are driven as single ended TTL to the scalar crate
         with edges ensured by tristating the drivers.  

Page 12: Prescaled FRED data output to Level 2 processor crate.
         Front panel 68 pin connectors with LVDS drivers. Unfortunatly
         will require a custom wired cable assembly.

Page 13: Input buffers and conector for J3 ( J5J6 ) backplane
         connector.  Uses prefred signal names from U of Chicago
         documentation.

Page 14: Xilinx Prescaling chips and configuration EPROM.  U157 also
         configures the Misc chip as well.  These chips generate the
         final fred L1 descision.

Page 15: Misc chip which handles many details of board operation.

------   Thurston Chandler 9/98
         Yale CDF Group