RXPT prototype schematic page descriptions

Page1:  J1, J2 J0 and front panel connectors
        Includes ESD strips, Geographic address pin logic,
        and the Power fusing and LED.
        Also RS-485 drivers and receivers for front panel connections
         to Trigger Supervisors.
* Note that front panel connectors will change in final version to
* correspond with the TS_2 front panel.
           
Page2: Clock switching / buffering, Front panel switches w/debouncing
       for reset and single step clock
       J5 J6  ( labelled J3 ) connector with buffers for 160
       return lines from backplane.

Page 3: VME interface featuring the Cypress SVIC chipset

Page 4: RXPT control chip ( Xilinx 4008 with serial prom )
        Handles board level registers and initialization.

Page 5: RXPT Device 1
         Set of 3 Xilinx FPGAs with associated parallel EPROM
        which can handle all 160 possible return lines of type
        Done -or- Error -or- Busy for a single detector partition.
*Note board features 4 independent devices. The following pages are
     very similar to this one.

Page 6: Device 2 as above
Page 7: Device 3 as above
Page 8: Device 4 as above
Page 9: Displays. LEDs, etc.

--Thurston Chandler 9/98
  Yale CDF Group