[Overview | TSI | TS | XPTs | FRED | Level2]
Yale Documents
Page Two:------Clocks and Buttons.
Page Three:-----VME Interface.
Page Four:------The "V" Chip.
Page Five:------XC1, XC2, XC3.
Page Six:-------TTL to ECL.
Page Seven:-----Crossbows.
Page Eight:------Level 1 Pipeline.
Page Nine:------Level 2 Buffers.
Page Ten:-------MLU (RAM).
Page Eleven:-----Scaler Drivers.
Page Twelve:-----Output to Level 2.
Page Thirteen:----J3 Inputs.
Page Fourteen:----Prescale Chips.
Page Fifteen:-----The Control Chip.
University of Chicago Documents
Specifications and Design of the Level 1 Calorimeter Trigger PreFred Modules for the Run II Upgrade