| Our group joined the
(ATLAS) in 2003.
The ATLAS detector is one of two next-generation detectors (along with
CMS) which are logical follow-ons to CDF and D0. As with CDF, ATLAS is
a general purpose, cylindrical geometry device used
to study collisions of protons on protons at a center-of-mass energy
of 14 TeV (compared to 2 TeV at our CDF experiment at FNAL).
It is located at the Large Hadron Collider (LHC) at
CERN in Geneva, Switzerland.
One of the strengths of the ATLAS detector is that it is a general-purpose device, allowing a broad range of physics to be studied. The LHC will be the highest energy accelerator in the world, making it the premier facility to search for new physics at the energy frontier. The LHC will open the opportunity before the end of this decade to begin to directly probe the 1 TeV energy regime where we hope and expect to discover the origin of electroweak symmetry breakdown. Whether the discovery comes in the form of a single Higgs boson, the observation of supersymmetric partners of standard model particles, manifestations of large extra dimensions, or the mysterious absence of any new phenomena at the predicted energy scale, the excitement in the field will be largely generated by the experimental program at this facility. |
The ATLAS TRT detector surrounds the inner silicon and pixel tracking volume of ATLAS. The TRT provides tracking and momentum determination as well as transition radiation information for electron identification, in both the central and forward portions of the ATLAS tracking system. The TRT detector will be important for allowing the determination of the sign of the electric charge for very high momentum tracks. The design of the detector optimizes the TR performance which will be an important handle for identifying electrons. The front-end electronics has been designed (by the U Penn group) to be robust and efficient even for the high rates of 20 MHz/channel expected in each of the straw drift-tube detector elements. The assembly of the straw drift-tube detectors in the radiation matrix is well underway, with 52544 straws in the axial barrel section and 319488 straws in the end cap sections. The end-cap has three types of ``wheels'', known as type A, B and C, with C being the outermost, high-eta detector elements. Recently, due to budget constraints, the C-wheels have been descoped from the baseline installation plan, and will possibly be added in at a later date. This has an impact on the aspects of the data acquisition system in which Yale is involved.
The first project Yale is involved in is the design and layout of the circuit boards for the barrel front-end electronics. Shortly before we joined the experiment, significant changes in the architecture of the front-end boards for the barrel module were made. There are 16 different designs needed for the barrel, corresponding to the various mechanical groupings of the straws in each module. There are three types of modules (types 1, 2 and 3), though the modules are subdivided into either 2 or 4 electrical units of varying shapes. The boards contain the readout chips attached to each straw (the Amplifier/Shaper/Discriminator/Baseline Restorer (ASDBLR) and Drift Time Measurement and Readout Chip (DTMROC) custom ICs design and built by U Penn).
The boards are quite challenging -- the final design is a 14-layer board with blind vias, sensitive analog circuitry on the side which holds the preamps connected to the individual straws, and high-speed digital signals on the other. Keeping data and clock pickup at the analog inputs to a minimum, keeping clean grounding for both analog and digital sections, all within an extremely limited amount of space and a difficult triangle geometry made the layout of the boards extremely time consuming. The project had only one engineer from Lund to layout all 16 boards which turned out to be on the critical path for an on-time installation of the ATLAS detector. We agreed to take on the layout of 6 of the boards, 2 of type-2 modules and 4 of the type-3 modules. The difficulty of the project is evident in that we submitted designs to 5 highly regarded firms in various countries, and only 1 ever managed to produce a working prototype. The current status is that the type 2 boards have been successfully prototyped and are ready for production, while the type 3 boards are just back from their prototype run and will be examined in the next two weeks.
The availability of these boards in time for the summer test beam at CERN (both TRT standalone and integrated with other ATLAS detectors) was crucial. The Yale boards are the only type 2 and 3 boards ready -- without these we would have only had one layer of TRT modules to be read out. Since one of the main goals of this (last) test beam is to study the integrated performance of an entire slice of the ATLAS detector, this was an important milestone to achieve.
For pictures of the mounting some of the Yale-designed Front-End boards, click here.
Finally, the performance of the Yale-designed boards is extremely promising -- they have the lowest noise of any front-end boards produced to date.
The second project is the design, production, and testing of the Readout Drivers (RODs). These 9U VME-based boards are responsible for the readout of the front-end electronics briefly described above. The RODs also zero-suppress, compress and reformat the data, then send it to the Readout Buffers (ROBs) for use in the L2 trigger, and possible output to the L3 trigger. A total of 256 RODs are needed for the full TRT system. However, with the staging of the C-wheels this number becomes 192. The original architecture for the DAQ system was predicated on reading out one phi-slice of the end-cap wheels, i.e. a wedge of A, B and C wheels, together. This data (from 1/32 of the end-cap) would end up together in one ROB, for ease of use in the L2 trigger. To save money on the staged C-wheel electronics requires a redesign of the readout architecture and granularity, and has repercussions throughout the trigger/DAQ chain. We have been reexamining these issues, taking into account advances in FPGA density and functionality.
We have examined the zero-suppression and compressability of the data from an information-theoretic point of view. Previous plans involves up to 8 different compression schemes, depending on the instantaneous luminosity of the beam. Further, lossy compression was envisioned for all but the lowest luminosity running. By studying the "entropy" of the data, i.e. the actual information content, we showed that a completely lossless compression scheme is possible, and fits well within the available bandwidth of the DAQ chain. Since the entropy of the data stream varies logarithmically with the complexity of the data, there is only modest growth in the data volume from low to high luminosity conditions, and one compression works scheme for both. This scheme also allows us to monitor the detector performance at a higher rate, with lower on-board resources necessary. With such ideas, and higher density FPGAs, halving the number of RODs needed seems quite possible (and perhaps even larger density improvements can be made). This will significantly reduce the cost of the back-end system, as well as making it easier to test and maintain the system in the future.